Apparatus and method for a memory storage cell leakage cancellation scheme
US6608786B2 · kind B2 · utility
11Cited by
9References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2001 |
| Grant date | Aug 19, 2003 |
| Priority date | — |
| Expiry date | Mar 30, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is described having a plurality of storage cells coupled between a first bit line and a second bit line. The apparatus also has a first transistor that pre-charges the first bit line and provides a first supply of current for one or more leakage currents drawn from the first bit line by any of the plurality of storage cells. The apparatus also has a second transistor that pre-charges the second bit line and provides a second supply of current for one or more leakage currents drawn from the second bit line by any of the plurality of storage cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.