Method and apparatus for correlating error model with defect data
US6610550B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2002 |
| Grant date | Aug 26, 2003 |
| Priority date | — |
| Expiry date | Apr 3, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54453
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus for correlating error data with detect data. A semiconductor wafer in a first lot is processed. Defect data based upon analysis of the processed semiconductor wafer is acquired. Electrical test data based upon analysis of the processed semiconductor wafer is acquired. The electrical test data is acquired by performing a wafer electrical testing process on the processed semiconductor wafer. The electrical test data is correlated with the defect data to produce correlated data. At least one of the following is performed: a yield prediction or the performance prediction of a second lot based upon the correlated data. The yield prediction comprises predicting a percentage yield of acceptable semiconductor wafers in the second lot. The performance prediction comprises predicting the performance of the acceptable semiconductor wafers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.