Integrated void-free process for assembling a solder bumped chip
US6610559B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2001 |
| Grant date | Aug 26, 2003 |
| Priority date | — |
| Expiry date | Nov 16, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/3489
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated void-free process has been developed for attaching a solder bumped chip to a substrate. The chip is first dipped in a tacky thermosettable flux, and the chip is mounted on the substrate. An underfill is dispensed along the edge of the chip The device is then sent into the reflow furnace to complete the underfilling (which optionally can be completed before reflow), solder reflowing and underfill curing. The flux also acts as a physical barrier minimizing, if not eliminating, the interference of filler on solder wetting and resulting metallurgical joints formed between the solder and the bond pads. The process allows for the integration of a void free conventional capillary flow underfilling process and a pre-deposited fluxing underfilling process by using a tacky thermosettable flux, avoiding the problems associated with each of the individual processes and requiring less time for the overall process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.