Field effect transistor with self alligned double gate and method of forming same

US6611023B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• William G. En · Sunnyvale, US
• Srinath Krishnan · Campbell, US

Key dates

• Filing date: May 1, 2001
• Grant date: Aug 26, 2003
• Expiry date: May 1, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6734

Abstract

A fully depleted silicon on insulator (SOI) field effect transistor (FET) includes a gate positioned above a channel region and an aligned back gate positioned below the channel region and the buried oxide later. Alignment of the back gate with the gate is achieved utilizing a disposable gate process and retrograde doping of the backgate.