Stacked multi-chip package structure with on-chip integration of passive component
US6611434B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2000 |
| Grant date | Aug 26, 2003 |
| Priority date | — |
| Expiry date | Oct 30, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/924
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked multi-chip package structure with on-chip integration of passive component is proposed, which is characterized in the mounting of passive component on a remaining surface area of the underlying semiconductor chip that is unoccupied by the overlying semiconductor chip, so that the overall package construction can be made more compact in size. The proposed package structure comprises: a substrate; a first semiconductor chip mounted over the substrate; a second semiconductor chip mounted over the first semiconductor chip; and at least one passive component mounted beside the second semiconductor chip and over the first semiconductor chip. The first and second semiconductor chips can be mounted by means of adhesive layers or flip chip technology. The passive component can be electrically coupled to the semiconductor chips through the use of wire-bonding technology (WBT) or surface-mount technology (SMT).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.