Method and apparatus for controlling and observing data in a logic block-based ASIC
US6611932B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2002 |
| Grant date | Aug 26, 2003 |
| Priority date | — |
| Expiry date | Jan 24, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318516
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system for testing an integrated circuit, and particularly a gate array, is disclosed which includes, prior to coupling the array to form a user-designed circuit, predesigned logic that enables testing of the user-designed circuit. The predesigned logic allows logic blocks in the array to operate in “freeze” mode or to operate in normal mode, where normal mode is defined by the user-designed circuit. When the logic blocks are selected to be frozen, the logic blocks behave as a series of daisy-chained master-slave flip-flops. In normal mode, a logic block can implement combinational, sequential, or other functions and still later be as a master-slave flip-flop. Moreover, each logic block is further equipped for addressable mode control, allowing selected logic blocks to be exercised in isolation once stimulus data is shifted in, simplifying test generation and improving fault coverage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.