Metallization process sequence for a barrier metal layer

US6613660B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Volker Kahlert · Dresden, DE
• Frank Koschinsky · Radebeul, DE
• Peter Hübler · Coswig, DE

Key dates

• Filing date: Apr 24, 2002
• Grant date: Sep 2, 2003
• Expiry date: Apr 24, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76843
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In an in situ damascene metallization process employing a barrier layer between the metal and the dielectric, the generation of voids, especially at the bottom of vias, can be significantly reduced or even completely avoided by maintaining the surface temperature below a critical temperature during deposition of the barrier material.