Frank Koschinsky
16Patents
4h-index
20Co-inventors
56Inventor score
Filing activity: Apr 11, 2002 → Sep 6, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6613660B2 | Metallization process sequence for a barrier metal layer | Electricity | 31 | Expired |
| US6964874B2 | Void formation monitoring in a damascene process | Electricity | 23 | Expired |
| US9177858B1 | Methods for fabricating integrated circuits including barrier layers for interconnect structures | Electricity | 23 | Active |
| US8053354B2 | Reduced wafer warpage in semiconductors by stress engineering in the metallization system | Emerging Cross-Sectional Technologies | 6 | Active |
| US8163571B2 | Multi-step deposition control | Electricity | 3 | Active |
| US8585877B2 | Multi-step deposition control | Electricity | 1 | Active |
| US9147618B2 | Method for detecting defects in a diffusion barrier layer | Electricity | 1 | Active |
| US8323989B2 | Test system and method of reducing damage in seed layers in metallization systems of semiconductor devices | Electricity | 1 | Active |
| US7820536B2 | Method for removing a passivation layer prior to depositing a barrier layer in a copper metallization layer | Electricity | 1 | Active |
| US9177826B2 | Methods of forming metal nitride materials | Electricity | 1 | Active |
| US8039400B2 | Reducing contamination of semiconductor substrates during BEOL processing by performing a deposition/etch cycle during barrier deposition | Emerging Cross-Sectional Technologies | 1 | Active |
| US8058081B2 | Method of testing an integrity of a material layer in a semiconductor structure | Electricity | 0 | Active |
| US6716650B2 | Interface void monitoring in a damascene process | Electricity | 0 | Expired |
| US10090195B2 | Method including a formation of a diffusion barrier and semiconductor structure including a diffusion barrier | Electricity | 0 | Active |
| US7063091B2 | Method for cleaning the surface of a substrate | Electricity | 0 | Expired |
| US9171754B2 | Method including an etching of a portion of an interlayer dielectric in a semiconductor structure, a degas process and a preclean process | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.