Ferroelectric transistor and memory cell configuration with the ferroelectric transistor

US6614066B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Reinhard Stengl · Stadtbergen, DE
• Hans Reisinger · Grünwald, DE
• Thomas Haneder · Hersbruck, DE
• Harald Bachhofer · Hersbruck, DE

Key dates

• Filing date: Apr 1, 2002
• Grant date: Sep 2, 2003
• Expiry date: Apr 1, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/701

Abstract

A first source-drain region, a channel region, and a second source-drain region are arranged one after another in a semiconductor substrate. At least the surface of the channel region and parts of the first source-drain region are covered by a dielectric layer. A ferroelectric layer is disposed on the surface of the dielectric layer between two polarization electrodes. A gate electrode is arranged on the surface of the dielectric layer. The thickness of the dielectric layer is dimensioned such that a remanent polarization of the ferroelectric layer, which is aligned between the two polarization electrodes, produces compensation charges in part of the channel region. The ferroelectric transistor is suitable as a memory cell for a memory cell configuration.