Dynamic scan chains and test pattern generation methodologies therefor
US6615380B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1999 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Dec 21, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/267
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
According to the present invention, during scan conversion, non-scan memory cells of a circuit design are replaced with scan cells to form a scan chain. The scan chain is transformed by the test synthesis tool of the present invention into dynamic scan chains with the addition of reconfiguration circuitry. The reconfiguration circuitry partitions the scan chain into multiple segments and enables each segment to be selectively “bypassed” (or deactivated) during test application. Shorter test patterns that are only pertinent to one or more segments are necessary, resulting in a reduction in overall test data volume and test application time. The present invention also provides a modified ATPG technique for generating test patterns for the dynamic scan chains.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.