Integrated circuit, test structure and method for testing integrated circuits

US6618303B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Arndt Gruber · Birkenfeld, DE
• Ralf Schneider · Birkenfeld, DE
• Bernhard Ruf · Sauerlach, DE
• Norbert Wirth · Unterschleißheim, DE

Key dates

• Filing date: Aug 13, 2001
• Grant date: Sep 9, 2003
• Expiry date: Oct 14, 2021

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2029/2602
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An electronic circuit in an integrated circuit having memory cells is described. The circuit permits information to be written to particular memory cells only once, so that subsequent writing to the particular memory cells is blocked. The circuit is used in a test structure for integrated circuits on a wafer. A method for testing integrated circuits on a wafer that are connected to a test apparatus is also described. Once the supply voltage to a first circuit to be tested has been turned on, a preliminary test is carried out to ascertain parameters that need to be set. The supply voltage is then applied to a next circuit to be tested, a preliminary test is carried out, and memory cells have information written to them, until the parameters have been set for all the connected circuits to be tested. The test apparatus then carries out the actual operational test in parallel for all the connected circuits to be tested.