Semiconductor memory device having row and column redundancy circuit and method of manufacturing the circuit

US6618306B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Thomas Böhm · Zorneding, DE
• Helmut Kandolf · Hersbruck, DE
• Stefan Lammers · Hersbruck, DE
• Zoltan Manyoki · Gatineau, CA

Key dates

• Filing date: Sep 9, 2002
• Grant date: Sep 9, 2003
• Expiry date: Sep 9, 2022

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C29/46
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A digital circuit configuration includes a memory matrix having M rows and N columns and P<M additional rows and Q<N additional columns, and an addressing device whose address connection contacts are sufficient precisely for addressing the M rows and N columns. To address the additional rows and columns as well, particularly, for test purposes, only a single control bit connection contact is provided with a changeover device responding to control bits from the control bit connection contact and from dedicated address connection contacts to associate applied address bits either with addressing of the M rows and N columns or the additional rows and columns. The numbers P and Q are chosen such that the addressing of P elements requires at least two bits fewer than the addressing of M elements, and such that the addressing of Q elements requires at least two bits fewer than the addressing of N elements.