Structure and methods for process integration in vertical DRAM cell fabrication
US6620676B2 · kind B2 · utility
7Cited by
14References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2001 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Jun 29, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.