Semiconductor trench device with enhanced gate oxide integrity structure
US6620691B2 · kind B2 · utility
16Cited by
12References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2001 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Nov 20, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A method for making trench DMOS is provided that improves the breakdown voltage of the oxide layer in a device having at least a first trench disposed in the active region of the device and a second trench disposed in the termination region of the device. In accordance with the method, mask techniques are used to thicken the oxide layer in the vicinity of the top corner of the second trench, thereby compensating for the thinning of this region (and the accompanying reduction in breakdown voltage) that occurs due to the two-dimensional oxidation during the manufacturing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.