DRAM with vertical transistor and trench capacitor memory cells and methods of fabrication

US6621112B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Venkatachalam C. Jaiprakash · Sunnyvale, US
• Mihel Seitz · Wappingers Falls, US
• Norbert Arnold · Pfalzgrafenweiler, DE

Key dates

• Filing date: Dec 6, 2000
• Grant date: Sep 16, 2003
• Expiry date: Dec 11, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/0385

Abstract

A semiconductor Dynamic Random Access Memory (DRAM) cell is fabricated using a vertical access transistor and a storage capacitor formed in a vertical trench. A Shallow Trench Isolation (STI) region is used as a masking region to confine the channel region of the access transistor, the first and second output regions of the access transistor, and a strap region connecting the second output region to the storage capacitor, to a narrow portion of the trench. The so confined second output region of the access transistor has reduced leakage to similar second output regions of adjacent memory cells. Adjacent memory cells can then be placed closer to one another without an increase in leakage and cross-talk between adjacent memory cells.