System for optimizing anti-fuse repair time using fuse ID
US6622270B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 13, 2001 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Dec 13, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for testing semiconductor memory chips, such as DRAMs, having a plurality of memory cells or bits. Each memory chip has a unique identifier stored in a database. Tests are performed on the memory chips and when a memory chip fails a test, the memory chip is placed in a repair bin and a test identifier is stored in the database in association with the memory chip identifier. In order to repair the memory chip, failed tests are read out of the database and such tests are again performed on the failed memory chip in order to determine which memory cell in the memory chip is faulty. The failed memory cells are then repaired.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.