Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure

US6624031B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Wagdi W. Abadeer · Jericho, US
• Eric Adler · Jericho, US
• Jeffrey S. Brown · Jeffersonville, US
• Robert J. Gauthier, Jr. · South Burlington, US
• Jonathan M. McKenna · Ann Arbor, US
• Jed H. Rankin · South Burlington, US
• Edward W. Sengle · South Burlington, US
• William R. Tonti · South Burlington, US

Key dates

• Filing date: Nov 20, 2001
• Grant date: Sep 23, 2003
• Expiry date: Dec 14, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may,be substituted for the diode. The use of the diode as an antifuse is also disclosed.