Low threshold voltage silicon-on-insulator clock gates
US6624663B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2001 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Nov 11, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock driver is disclosed that minimizes propagation delay, and thus improves the integrity of a clock distribution network. The clock driver preferably is implemented with silicon-on-insulator (SOI) technology, and comprises an inverter with an nFET and pFET that are body-connected. The body connection serves to reduce the body voltage of the pFET, while increasing the body voltage of the nFET. This shifting of the voltage reduces the voltage threshold differential for both the nFET and pFET, which translates into a design that experiences less propagation delay due to voltage variations and fluctuations. If desired, the body voltages may be slightly offset from each other by placing one or more voltage drop transistors in the conductive path between the bodies of the nFET and pFET. In addition, the present invention may be used to design a programmable inverter that can operate in a low power mode, or in a high precision mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.