Method of forming dual-damascene interconnect structures employing low-k dielectric materials
US6627539B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 1998 |
| Grant date | Sep 30, 2003 |
| Priority date | — |
| Expiry date | Sep 9, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Interconnects in sub-micron and sub-half-micron integrated circuit devices are fabricated using a dual damascene process incorporating a low-k dielectric. A dual-damascene structure can be implemented without the necessity of building a single damascene base, and without CMP of the low-k dielectric. This structure simplifies the manufacturing process, reduces cost, and effectively reduces intra-level and inter-level capacitance, resistivity, and noise related to substrate coupling. In accordance with a further aspect of the present invention, a modified silicon oxide material such as silsesquioxane is used for the low-k dielectric in conjunction with silicon dioxide cap layers, allowing an improved process window and simplifying the etching process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.