Insulation of an MRAM device through a self-aligned spacer
US6627913B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 10, 2001 |
| Grant date | Sep 30, 2003 |
| Priority date | — |
| Expiry date | Sep 10, 2021 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB82Y10/00
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A memory for an integrated circuit and method of fabricating same are provided, comprising providing an array of magnetic memory devices, preferably TMR junctions, that are configured as individual studs and protrude from a substrate. A layer of insulating spacer material is deposited over the array of magnetic memory devices, and a spacer etch is performed to remove the spacer material preferentially from the top surfaces of the magnetic memory devices and from substrate surface areas between the magnetic memory devices. Preferably, the insulating spacer material is low k and/or a barrier to outdiffusion of species from the TMR junctions. Examples include silicon carbide (BLOk™), low temperature silicon nitride or diamond-like carbon. In another embodiment, the insulating spacer material is also a magnetic material and may comprise magnesium-zinc ferrites or nickel-zinc ferrites.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.