Semiconductor memory array of floating gate memory cells with control gates protruding portions
US6627946B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 26, 2001 |
| Grant date | Sep 30, 2003 |
| Priority date | — |
| Expiry date | Jul 29, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6891
Abstract
A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction. Floating gates are formed in each of the active regions. In the row direction, trenches are formed that include indentations. The trenches are filled with a conducting material to form blocks of the conducting material that constitute control gates. The trench indentations result in the formation of protruding portions on the control gates that extend over the floating gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.