Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cells
US6629304B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2001 |
| Grant date | Sep 30, 2003 |
| Priority date | — |
| Expiry date | Dec 5, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Cell overlap is removed from rows during a cell placement procedure for an integrated circuit chip. The rows are partitioned into subrows so that cells in each subrow have a common characteristic vector. Cell overflow is removed from each of the subrows by moving a cell of an overflowed row or exchanging two cells, at least one of which is in the overflowed subrow. The half-cells of the dual height cells are moved to cell positions in a suitable pair of rows based on a calculated movement penalty. The movement is accomplished to align the half-cells and minimize the penalty. In preferred embodiments, the process is carried out by a computer under control of a computer program.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.