Method of fabricating double densed core gates in sonos flash memory
US6630384B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2001 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | Oct 5, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; forming a first set of memory cell gates over the charge trapping dielectric in the core region; forming a conformal insulation material layer around the first set of memory cell gates; and forming a second set of memory cell gates in the core region, wherein each memory cell gate of the second set of memory cell gates is adjacent to at least one memory cell gate of the first set of memory cell gates, each memory cell gate of the first set of memory cell gates is adjacent at least one memory cell gate of the second set of memory cell gates, and the conformal insulation material layer is positioned between each adjacent memory cell gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.