Mark T. Ramsbey
159Patents
30h-index
130Co-inventors
93Inventor score
Filing activity: Jun 7, 1995 → Sep 30, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6674138B1 | Use of high-k dielectric materials in modified ONO structure for semiconductor devices | Electricity | 256 | Expired |
| US6642573B1 | Use of high-K dielectric material in modified ONO structure for semiconductor devices | Emerging Cross-Sectional Technologies | 174 | Expired |
| US6912163B2 | Memory device having high work function gate and method of erasing same | Electricity | 113 | Expired |
| US6803272B1 | Use of high-K dielectric material in modified ONO structure for semiconductor devices | Electricity | 108 | Expired |
| US7115469B1 | Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process | Electricity | 95 | Expired |
| US6436768B1 | Source drain implant during ONO formation for improved isolation of SONOS devices | Electricity | 94 | Expired |
| US6541816B2 | Planar structure for non-volatile memory devices | Emerging Cross-Sectional Technologies | 83 | Expired |
| US6440797B1 | Nitride barrier layer for protection of ONO structure from top oxide loss in a fabrication of SONOS flash memory | Emerging Cross-Sectional Technologies | 79 | Expired |
| US7018868B1 | Disposable hard mask for memory bitline scaling | Electricity | 72 | Expired |
| US6670241B1 | Semiconductor memory with deuterated materials | Electricity | 66 | Expired |
| US6639271B1 | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same | Electricity | 57 | Expired |
| US6468865B1 | Method of simultaneous formation of bitline isolation and periphery oxide | Electricity | 53 | Expired |
| US6927145B1 | Bitline hard mask spacer flow for memory cell scaling | Electricity | 52 | Expired |
| US6433383B1 | Methods and arrangements for forming a single interpoly dielectric layer in a semiconductor device | Electricity | 46 | Expired |
| US6630383B1 | Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer | Electricity | 46 | Expired |
| US6630384B1 | Method of fabricating double densed core gates in sonos flash memory | Electricity | 44 | Expired |
| US6555436B2 | Simultaneous formation of charge storage and bitline to wordline isolation | Emerging Cross-Sectional Technologies | 44 | Expired |
| US6001713A | Methods for forming nitrogen-rich regions in a floating gate and interpoly dielectric layer in a non-volatile semiconductor memory device | Electricity | 42 | Expired |
| US7033957B1 | ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices | Emerging Cross-Sectional Technologies | 42 | Expired |
| US6566194B1 | Salicided gate for virtual ground arrays | Electricity | 42 | Expired |
| US6958511B1 | Flash memory device and method of fabrication thereof including a bottom oxide layer with two regions with different concentrations of nitrogen | Electricity | 42 | Expired |
| US5907781A | Process for fabricating an integrated circuit with a self-aligned contact | Electricity | 41 | Expired |
| US6617215B1 | Memory wordline hard mask | Electricity | 39 | Expired |
| US6653190B1 | Flash memory with controlled wordline width | Electricity | 38 | Expired |
| US6680509B1 | Nitride barrier layer for protection of ONO structure from top oxide loss in fabrication of SONOS flash memory | Emerging Cross-Sectional Technologies | 38 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.