Self-aligned PECVD etch mask
US6630410B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2002 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | Aug 13, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24537
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming an etched feature in a substrate such as an insulator layer of a semiconductor wafer is provided. In one embodiment, the method includes initially etching a substrate layer using a photoresist or other masking layer to form the etched feature (e.g., opening) to a selected depth, and depositing a self-aligning mask layer for a continued etch of the formed feature. In another embodiment of the method, the self-aligned mask is deposited onto a substrate having an etched opening or other feature, to protect the upper surface and corners of the substrate and sidewalls of the feature while the bottom portion of the opening is cleaned or material at the bottom portion of the opening is removed. The present methods utilize the height difference between the bottom portion of the feature and the surface of the substrate to selectively deposit a self-aligning mask layer relative to a pre-formed opening or other feature, for example, to extend an opening to a depth that an original photomask thickness cannot support.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.