Method and system for performing deterministic analysis and speculative analysis for more efficient automatic test pattern generation
US6631344B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 1999 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | Mar 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/263
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer implemented synthesis system, a method of generating a test pattern for use in testing device with ATE (automated test equipment). The computer implemented steps of receiving a netlist specification representing a design to be realized in physical form and storing the netlist specification in a computer memory unit, and simulating the netlist using the computer implemented synthesis system. Using the simulation instantiated within the synthesis system, deterministic test pattern generation is performed to obtain a first portion (partial) of a test pattern. The test pattern is operable to detect a fault in the circuit netlist once speculative test pattern generation is performed to obtain a remaining portion of the test pattern. The first portion and the remaining portion of the test pattern comprise a test vector operable to detect the fault when used with automated test equipment for testing a device resulting from the design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.