SOI FET and method for creating FET body connections with high-quality matching characteristics and no area penalty for partially depleted SOI technologies
US6635518B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2001 |
| Grant date | Oct 21, 2003 |
| Priority date | — |
| Expiry date | May 30, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
Methods and apparatus are provided for creating field effect transistor (FET) body connections with high-quality matching characteristics and no area penalty for partially depleted silicon-on-insulator (SOI) circuits. The FET body connections are created for partially depleted silicon-on-insulator (SOI) technologies by forming adjacent FET devices inside a shallow trench shape. The adjacent FET devices share a common diffusion area, such as source or drain. Selectively spacing apart adjacent gate lines form an underpath connecting bodies of the adjacent FET devices. The underpath is defined by forming an undepleted region on top of a buried oxide layer. The adjacent polysilicon gate lines are selectively spaced apart to define a depth of depletion in a shared diffusion region for creating the underpath. Also, adjacent FET devices with connecting bodies can be built by adding an ion implant masking step to the fabrication process. This masking step changes the depletion depth under the shared diffusion area. As a result an underpath body connection is formed. Such methods of building adjacent FET devices with an underpath connecting the two device bodies can be used in combination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.