Structure and method for dual work function logic devices in vertical DRAM process

US6635526B1 · kind B1 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Rajeev Malik · Pleasantville, US
• Rama Divakaruni · Ossining, US
• Rajesh Rengarajan · Fishkill, US

Key dates

• Filing date: Jun 7, 2002
• Grant date: Oct 21, 2003
• Expiry date: Jun 7, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/665

Abstract

Dual work function transistors are provided in a cmos support area 14 with an embedded vertical dram array 12. A wordline layer 54, and nitride cap layer 56 cover the dram array 12 and a gate oxide layer 42 and an undoped polysilicon layer 44 cover the support area 14. A common mask is applied and patterned over the substrate to define the wordlines line structures in the dram array 12 and the gate structures in the support 14. The unwanted portions of the layers 54, 56, 42 and 44 are removed by etching.