Patent · US Expired

Method of producing alignment marks

US6635567B2 · kind B2 · utility

8Cited by

10References

17Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Eva Ebertseder · Dresden, DE
Matthias Lehr · Dresden, DE
Torsten Werneke · Dresden, DE
Jochen Hanebeck · Ottobrunn, DE
Jürgen Pahlitzsch · Wallroda, DE

Key dates

Filing date	Jan 11, 2001
Grant date	Oct 21, 2003
Priority date	—
Expiry date	Mar 29, 2021

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Alignment marks (overlay marks or alignment markers) are produced in a semiconductor structure with integrated circuits. Contact holes and alignment trenches are etched into an insulator layer and in each case open out at a first metal layer at their undersides. Metal is deposited into the alignment trenches and the contact holes. With a subsequent chemical mechanical polishing procedure, the metal areas are lowered in the region of the alignment trenches and form profiles for the alignment marks in a second metal layer, which is deposited on the insulator layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.