Semiconductor integrated circuit device
US6635937B2 · kind B2 · utility
7Cited by
3References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 23, 2002 |
| Grant date | Oct 21, 2003 |
| Priority date | — |
| Expiry date | Jun 23, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
Abstract
To improve performance, a capacitor is provided between storage nodes of an SRAM and a device having an analog capacitor on a single substrate, a plug is formed in a silicon oxide film on a pair of n channel type MISFETs in a memory cell forming area, and a local wiring LIc for connecting respective gate electrodes and drains of the pair of n channel type MISFETs is formed over the silicon oxide film and the plug. Thereafter, a capacitive insulating film and an upper electrode are formed over the local wiring LIc.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.