Method of manufacturing semiconductor device with high and low breakdown transistors

US6638804B2 · kind B2 · utility

Assignee

• SEIKO EPSON CORPORATION · JP

Inventors

• Atsushi Kanda · Tokushima, JP
• Yasushi Haga · Sakata, JP

Key dates

• Filing date: Oct 17, 2002
• Grant date: Oct 28, 2003
• Expiry date: Oct 17, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

Among first and second oxide films 110 and 112 formed on a substrate 100, the oxide film in a low-breakdown-voltage transistor area LV is all etched off, while the whole surface of the oxide film in a high-breakdown-voltage transistor area HV is left intact. A sixth oxide film 119 to define a side wall is subsequently formed on the whole surface of the substrate 100, and a resist R17 is formed over the whole high-breakdown-voltage transistor area HV. Over-etching of the low-breakdown-voltage transistor area LV is carried out to make the surface of the substrate 100 exposed and to define the side wall only in the low-breakdown-voltage transistor area LV. The oxide film 119 is made to remain in the high-breakdown-voltage transistor area HV. Non-required portions of the oxide films 119 and 112 are then etched off with a resist R15B. This causes a drain-source forming region, which is expected to form a drain area and a source area, to be open in an element forming region in a high-breakdown-voltage nMOS area HVn. The resist R15B is not removed but is used continuously, and an n-type impurity ion is implanted into the open drain-source forming region. This arrangement enables both a hi…