Elimination of narrow device width effects in complementary metal oxide semiconductor (CMOS) devices
US6638832B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2000 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Dec 21, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Neutral conductivity ions, preferably germanium, are implanted through the oxide of a metal oxide semiconductor after isolation formation to provide a nearly constant threshold voltage for transistor operation independent of transistor channel width as device geometries are scaled down in size. The present invention sets forth a method for fabricating a metal oxide semiconductor (MOS) structure that controls threshold voltage Vt in the structure, the method including generating an isolation region of the semiconductor structure on a major surface of a silicon substrate, growing a thin oxide on the major surface of the semiconductor structure, implanting a large diameter neutral conductivity type ion into the major surface of the semiconductor structure through the thin oxide, annealing the semiconductor structure having the neutral conductivity ion implanted therein, and processing the semiconductor structure to create MOS devices having a near constant threshold voltage over a range of device channel widths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.