Method for forming a silicide gate stack for use in a self-aligned contact etch
US6638843B1 · kind B1 · utility
6Cited by
28References
34Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 23, 2000 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Mar 23, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0225
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a gate stack having a silicide layer that can subsequently undergo a SAC etch is disclosed. The present method provides a layer of insulating material on top of the silicide layer. The insulating material is sufficient to protect the gate stack, including the silicide layer when the low-resistance gate stack is used in subsequent self-aligned contact etch processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.