Semiconductor device having a vertical semiconductor element
US6639260B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2001 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Dec 17, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/127
Abstract
A vertical type MOS field effect transistor has a super junction structure between a source electrode and an N+-type drain region. The super junction structure is constituted by a plurality of P-type single crystal silicon regions and a plurality of N-type single crystal silicon regions. Each of the plurality of P-type single crystal silicon regions and each of the plurality of N-type single crystal silicon regions are arrayed alternately. The super junction has two parts, that is, a cell forming region where a MOS structure is disposed and a peripheral region located at a periphery of the cell forming region. The source electrode contacts one of the P-type single crystal silicon regions in the peripheral region while disposed away from an end portion of the peripheral region that is located at an outermost in the peripheral region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.