Redundancy circuit of semiconductor memory device
US6639854B2 · kind B2 · utility
10Cited by
1References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2001 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Jan 24, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having a redundancy circuit, includes a normal memory cell array unit, a redundancy memory cell array unit for recovering defective cells of the normal memory cell array unit, and a memory driving unit for operating the normal memory cell adjacent to the redundancy memory cell array unit immediately after a word line move time ‘tcycle’ is elasped by using address data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.