Silicide MOSFET architecture and method of manufacture
US6642119B1 · kind B1 · utility
29Cited by
8References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2002 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Aug 20, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/952
Abstract
The present invention relates to a method of forming a transistor and a transistor structure. The invention comprises forming the transistor using a double silicide process which reduces resistance and reduces the floating-body-effect when employed in conjunction with SOI type device architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.