Method for dicing a semiconductor wafer
US6642127B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2001 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Oct 19, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/78
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for dicing a semiconductor wafer using a plasma etch process. The method begins by applying a patterned mask to the integrated circuits on a wafer. The pattern covers the circuits and exposes the streets between the dice. Next, the method deposits a uniform layer of adhesive material upon a carrier wafer. The wafer to be diced is affixed to the carrier wafer via the adhesive material that is sandwiched between the bottom surface of the wafer to be diced and the top surface of the carrier wafer. The combination assembly of the carrier wafer, adhesive and wafer to be diced is placed in an etch reactor that is capable of etching silicon. When the reactive gas is applied to the combination assembly, the etch plasma will consume the unprotected silicon within the streets and dice the wafer into individual integrated circuit chips. The carrier wafer is then removed from the etch chamber with the dice still attached to the adhesive layer. A well-known process is used to remove the adhesive material as well as any mask material and detach the dice from the carrier wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.