RELACS shrink method applied for single print resist mask for LDD or buried bitline implants using chemically amplified DUV type photoresist
US6642148B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 19, 2002 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Apr 24, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention generally relates to a method of forming a graded junction within a semiconductor substrate. A first masking pattern having a first opening characterized by a first lateral dimension is formed over the semiconductor substrate. The semiconductor substrate is doped with a first dopant, using the first masking pattern as a doping mask, thereby forming a first dopant region in the semiconductor substrate underlying the first opening. The first masking pattern is swelled to decrease the first lateral dimension of the first opening to a second lateral dimension. The semiconductor substrate is then doped with a second dopant, using the swelled first masking pattern as a doping mask, thereby forming a second dopant region in the semiconductor substrate, and furthermore defining a graded junction within the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.