MOSFET with a thin gate insulating film
US6642560B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2002 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Jun 4, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrata via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (Tox) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or lass than 0.3 &mgr;m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.3 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.