Wire bonding method and semiconductor package manufactured using the same
US6642610B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2000 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Dec 20, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package including plural semiconductor chips, and a wire bonding step for electrically interconnecting the semiconductor chips, are disclosed. In an exemplary method, a substrate is provided. Conductive circuit patterns are provided outside of a chip mounting region of the substrate, and conductive transfer patterns are provided proximate to the chip mounting region. Chips are placed in the chip mounting region. Conductive wires are bonded between input/output pads of a first chip and respective transfer patterns, and other conductive wires are bonded between input/output pads of a second chip and the same transfer patterns, thereby electrically connecting respective input/output pads of the two chips through a pair of bond wires and an intermediate transfer pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.