Byung Joon Han
72Patents
22h-index
60Co-inventors
91Inventor score
Filing activity: Jun 16, 1994 → Jul 1, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5866939A | Lead end grid array semiconductor package | Electricity | 296 | Expired |
| US5608262A | Packaging multi-chip modules without wire-bond interconnection | Electricity | 269 | Expired |
| US5646828A | Thin packaging of multi-chip modules with enhanced thermal/power management | Electricity | 223 | Expired |
| US6861288B2 | Stacked semiconductor packages and method for the fabrication thereof | Electricity | 159 | Expired |
| US5473512A | Electronic device package having electronic device boonded, at a localized region thereof, to circuit board | Electricity | 130 | Expired |
| US6462274B1 | Chip-scale semiconductor package of the fan-out type and method of manufacturing such packages | Electricity | 78 | Expired |
| US6150709A | Grid array type lead frame having lead ends in different planes | Electricity | 76 | Expired |
| US7372141B2 | Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides | Electricity | 59 | Expired |
| US7364945B2 | Method of mounting an integrated circuit package in an encapsulant cavity | Electricity | 57 | Expired |
| US7429787B2 | Semiconductor assembly including chip scale package and second substrate with exposed surfaces on upper and lower sides | Electricity | 54 | Expired |
| US6414396B1 | Package for stacked integrated circuits | Electricity | 54 | Expired |
| US5858815A | Semiconductor package and method for fabricating the same | Electricity | 52 | Expired |
| US7309913B2 | Stacked semiconductor packages | Electricity | 52 | Expired |
| US7435619B2 | Method of fabricating a 3-D package stacking system | Electricity | 40 | Active |
| US5767447A | Electronic device package enclosed by pliant medium laterally confined by a plastic rim member | Electricity | 38 | Expired |
| US5834160A | Method and apparatus for forming fine patterns on printed circuit board | Electricity | 37 | Expired |
| US6642610B2 | Wire bonding method and semiconductor package manufactured using the same | Electricity | 36 | Expired |
| US8643163B2 | Integrated circuit package-on-package stacking system and method of manufacture thereof | Electricity | 30 | Active |
| US6020219A | Method of packaging fragile devices with a gel medium confined by a rim member | Electricity | 27 | Expired |
| US7733661B2 | Chip carrier and fabrication method | Emerging Cross-Sectional Technologies | 26 | Active |
| US6630373B2 | Ground plane for exposed package | Electricity | 25 | Expired |
| US8378476B2 | Integrated circuit packaging system with stacking option and method of manufacture thereof | Electricity | 23 | Active |
| US8309397B2 | Integrated circuit packaging system with a component in an encapsulant cavity and method of fabrication thereof | Electricity | 22 | Active |
| US5977624A | Semiconductor package and assembly for fabricating the same | Electricity | 21 | Expired |
| US6858470B1 | Method for fabricating semiconductor packages, and leadframe assemblies for the fabrication thereof | Electricity | 19 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.