Method for operating a multi-level memory cell
US6643170B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2001 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Nov 20, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for operating a memory cell of a multi-level NROM is described. The memory cell of the multi-level NROM comprises a nitride layer, wherein the nitride layer comprises a plurality of charge-trapping regions to store locally a plurality of charges as the first bit memory and the second bit of memory. The stored charges of the second bit of memory forms an electrical barrier, which in turns affects the size of the threshold electric current of the first bit. The different threshold electrical currents of the first bit, which are affected by the size of the electrical barrier, define the various memory states of the memory cell of the multi-level NROM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.