Method for erasing a memory cell
US6643181B2 · kind B2 · utility
107Cited by
125References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2001 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Oct 24, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for erasing a non-volatile memory cell array, the method including applying an erase pulse to at least one bit of at least one memory cell of the array, erase verifying the at least one bit with a first erase verify level, and if the bit has passed the first erase verify level, applying at least one more erase pulse to the at least one bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.