Method for repairing over-erasure of fast bits on floating gate memory devices
US6643185B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2002 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Aug 7, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for repairing over-erasure of floating gate memory devices. Specifically, one embodiment of the present invention discloses a method for performing a program disturb operation on an array of memory cells for repairing over-erasure of fast bits. The program disturb operation is applied simultaneously to the entire array making it compatible with channel erase schemes. The fast bits are programmed back to a normal state above 0 Volts by applying a substrate voltage to a substrate common to the array of memory cells. A gate voltage is applied to a plurality of word lines coupled to control gates of said array of memory cells. A program pulse time for applying voltages ranges from approximately 10 microseconds to 1 second. A voltage differential between a control gate and the substrate in a memory cell is in the range of approximately 9 Volts to about 20 Volts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.