Bus system optimization
US6643787B1 · kind B1 · utility
313Cited by
46References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 19, 1999 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Oct 19, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus system comprising a master connected to one or more slave devices via a bus is disclosed. The bus system is able to effectively communicate control information during a calibration phase and to individually determine appropriate timing and/or voltage offsets for each slave device. The offsets are used to optimize transfer timing (including duty cycle characteristics), signal equalization, and voltage levels for data exchanged between the master and the slave devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.