Method for forming trench MOSFET device with low parasitic resistance

US6645815B2 · kind B2 · utility

Assignee

• General Semiconductor, Inc. · US

Inventors

• Fwu-Iuan Hshieh · Saratoga, US
• Koon Chong So · Fremont, US
• John Amato · Tracy, US
• Brian Pratt · Tracy, US

Key dates

• Filing date: Nov 20, 2001
• Grant date: Nov 11, 2003
• Expiry date: Nov 20, 2021

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S148/126

Abstract

A method is provided for forming shallow and deep dopant implants adjacent source regions of a first conductivity type within an upper portion of an epitaxial layer in a trench MOSFET device. The method comprises: (a) forming a patterned implantation mask over the epitaxial layer, wherein the patterned implantation mask comprises a patterned insulating region and covers at least a portion of the source regions, and wherein the patterned implantation mask has apertures over at least portions of the epitaxial layer adjacent the source regions; (b) forming shallow dopant regions by a process comprising: (1) implanting a first dopant of a second conductivity type at a first energy level within an upper portion of the epitaxial layer through the apertures and (2) diffusing the first dopant at elevated temperatures to a first depth from an upper surface of the epitaxial layer; (c) forming deep dopant regions by a process comprising: (1) implanting a second dopant of the second conductivity type at a second energy level within an upper portion of the epitaxial layer through the apertures and (2) diffusing the second dopant at elevated temperatures to a second depth from the upper surface …