Methods of reading ferroelectric memory cells
US6646906B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 13, 2003 |
| Grant date | Nov 11, 2003 |
| Priority date | — |
| Expiry date | Jan 13, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Bi-state ferroelectric-MOS (FMOS) capacitors are adapted for use in memory cells of a memory device. Bi-state ferroelectric memory cells have a bottom plate of a capacitor coupled to a first source/drain region of a pass transistor, a gate of the pass transistor coupled to a word line, and a second source/drain region of the pass transistor coupled to a bit line. A plate line is coupled to the top plate of the capacitor to facilitate programming of the polarization state of a ferroelectric portion of the capacitor. The polarization state of the ferroelectric portion of the capacitor causes a depletion or accumulation of electrons in the bottom plate of the capacitor, thus altering its capacitance value. The resulting capacitance value may be sensed without causing a polarization reversal of the ferroelectric portion of the capacitor. Accordingly, bi-state ferroelectric memory cells of the various embodiments function as non-volatile memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.