Compare branch instruction pairing within a single integer pipeline
US6647489B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2000 |
| Grant date | Nov 11, 2003 |
| Priority date | — |
| Expiry date | Jan 26, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are provided for executing a combined compare-and-branch operation in a single integer pipeline microprocessor. Typically, the compare-and-branch operation is specified by two macro instructions. The first macro instruction, a compare macro instruction, directs the microprocessor to compare two operands, resulting in the update of a flags register to describe various attributes of the comparison result. The second macro instruction, a conditional jump macro instruction, directs the microprocessor to examine the flags register and to branch program control to a target address if a prescribed condition is met. The apparatus has translation logic that combines the compare macro instruction and the conditional jump macro instruction into a single compare-and-branch micro instruction. The single compare-and-branch micro instruction directs the microprocessor to make the comparison and to perform a conditional branch based upon a result of the comparison. The apparatus also has execute logic that is coupled to the translation logic. The execute logic makes the comparison and generates the result. Jump resolution logic in a stage following the execute logic accesse…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.