Photoimageable material patterning techniques useful in fabricating conductive lines in circuit structures
US6649515B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1998 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Dec 4, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an interconnection including the steps of depositing a first masking material over a first conductive region of an integrated circuit substrate and depositing a dielectric material over the first masking material. The method also includes forming a via through the dielectric material to expose the first masking material and a second masking material is deposited in a portion of the via. A trench is formed in the dielectric material over a portion of the via and the second masking material is removed from the via. The via is then extended through the first masking material and a conductive material is deposited in the via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.