Semiconductor package with stacked chips
US6650006B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2001 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Aug 3, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package with stacked chips is proposed, in which a first chip mounted on and electrically connected to a chip carrier is attached with a rigid interposer thereto, while the rigid interposer has a second chip disposed thereon in a manner that the rigid interposer is interposed between the first chip and the second chip. With the use of the rigid interposer, the second chip stacked on the first chip can be positioned in planarly parallel to the chip carrier, allowing bonding wires for electrically connecting the second chip to the chip carrier to be bonded completely. Moreover, the second chip has portions thereof not located right above the first chip to be firmly supported by the rigid interposer, and thus the second chip can be prevented from cracking in the wire bonding process. Furthermore, on the chip carrier there is formed an encapsulant for encapsulating the first chip, the second chip and part of the chip carrier where the first and second chips are electrically connected thereto,
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.